Design and Implementation of Phase Modulation using PLL for Polar Transmitter
Kushal M L1, V Venkateswarlu2
1Mr. Kushal M L is a student at VLSI and Embedded System, VTU Extension Center, UTL Technologies Ltd., Bangalore, Karnataka, India.
2Dr. V Venkateswarlu is The Principal, and Professor at VLSI and Embedded System, VTU Extension Center, UTL Technologies Ltd., Bangalore, Karnataka, India.
Manuscript received on November 09, 2013. | Revised Manuscript Received on November 20, 2013. | Manuscript published on November 20, 2013. | PP: 35-41 | Volume-1, Issue-12, November 2013. | Retrieval Number: L03621111213/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper the phase modulation of polar transmitter has been implemented. The circuit for implementing phase modulation consists of Phase Lock Loop (PLL), Sigma Delta Modulator (SDM) and differentiator. The input signal is applied at the differentiator which will convert phase component to the frequency of the signal. The obtained frequency signal is given to the SDM which will convert the analog signal to the digital signals. The SDM should have four bits of resolution, equivalently 36 dB signal-to-noise-and-distortion-ratio (SNDR) for a 200 kHz bandwidth. For supply voltages from 2.5 V to 3 V, the current supply is desired to be less than 20 mA. The PLL consists of the reference signal of 125MHz, and output voltage around 2-3GHz with the VCO gain of 0.277GHz/V. The circuit of PLL, SDM and differentiator are implemented on the Cadence Virtuoso platform.
Keywords: Polar transmitter, phase modulation, Phase lock loop, Sigma delta modulator, differentiator.