Implementation of UART with BIST Technique in FPGA
Bibin M C1, Premananda B S2
1Bibin MC, M-Tech, VLSI Design and Embedded Systems, VTU Extension Centre, UTL Technologies Ltd., Bangalore, India.
2Premananda B.S., Asst. Prof., VLSI Design and Embedded Systems, VTU Extension Centre, UTL Technologies Ltd., Bangalore, India.
Manuscript received on July 03, 2013. | Revised Manuscript Received on July 19, 2013. | Manuscript published on July 20, 2013. | PP: 13-17 | Volume-1, Issue-8, July 2013. | Retrieval Number: H0256071813/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART), mostly used for short distance, low speed, low cost data exchange between processor and peripherals. UART allows full duplex serial communication link, and is used in data communication and control system. There is a need for realizing the UART function in a single or a very few chips. Further, design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, there is a need to ensure the data transfer is error proof. This paper targets the introduction of Built-in self test (BIST) and Status register to UART, to overcome the above two constraints of testability and data integrity. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA. The results indicate that this model eliminates the need for higher end, expensive testers and thereby it can reduce the development time and cost.
Keywords: UART, BIST, Error check, Status register, LFSR.