A Study Single Electron Transistor in Neural Network, Nanotechnology and Memory Design
Shivani Chauhan
Ms Shiwani chauhan, Department of ECE, KIIT College Of Engineering, Sohna Road, Gurgaon, India.
Manuscript received on April 07, 2013. | Revised Manuscript Received on April 19, 2013. | Manuscript published on April 20, 2013. | PP: 23-26 | Volume-1, Issue-5, April 2013. | Retrieval Number: E0205041513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: To avail the practical approach for low dimension designing of electronic chips , SET is being used on the highest concern to provide nanotechnology . Now in current days , artificial neural networks is playing important roll for the accuracy and less time response . A computer memory which is basically based on this property would be ability to retain information in case if processor it self powered off . SET is to be considered as elements for future low power , high density integrated circuits reason for this of their the potential to involving only few electrons for ultra low power . In this paper we express the study of single electron transistor being used in nanotechnology , artificial neural network & memory designing . the operation as single electron transistor with it’s history is mentioned included with advantages and disadvantage of SET.
Keywords: Operation of set , Nanotechnology , Neural Network & Current Standards.