A Novel Method of Diode Clamped Multi-Level Inverter using PWM Technique
N. Mohan Teja1, R S Ravi Sankar2, P. Harsha3, V. Uma Shankar4
1N. Mohan Teja, Vignan’s Institute of Information Technology, Duvvada, India.
2R S Ravi Sankar, Vignan’s Institute of Information Technology, Duvvada, India.
3P. Harsha, Vignan’s Institute of Information Technology, Duvvada, India.
4V. Uma Shankar Vignan’s Institute of Information Technology, Duvvada, India.
Manuscript received on March 07, 2014. | Revised Manuscript Received on March 15, 2014. | Manuscript published on March 20, 2014. | PP: 9-12 | Volume-2, Issue-4, March 2014. | Retrieval Number: D0416032414/2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This Paper presents a novel method of Diode clamped Multi Level Inverter, which works without series association the clamping diodes. The conventional diode clamping inverter suffers from such problems as dc link unbalance, indirect clamping of the inner devices, turn-on snubbing of the inner dc rails as well as series association of the clamping diodes etc. It is due largely to these problems that the application of the conventional diode clamping inverter in practice has been deterred, in spite of the growing discussion in the literature. An auxiliary resistive clamping network solving the indirect clamping problem of the inner devices is also discussed for both the new and conventional diode clamping inverter. Operation principle, clamping mechanism, auxiliary clamping as well as experimentation are presented.
Keywords: Clamping Diodes, DC Link Unbalance, Multi Level Inverter ,Pulse Width Modulation.