Various Power Dissipation Techniques for CMOS Inverter
R. Prakash Rao
Dr. R. Prakash Rao, Associate Professor, Department of Electronics and Communication Engineering, Matrusri Engineering College, Saidabad (Hyderabad)-500059, India.
Manuscript received on June 02, 2018. | Revised Manuscript received on June 18, 2018. | Manuscript published on October 20, 2018.| PP: 12-14 | Volume-4 Issue-10, June 2018. | Retrieval Number: J08190641018/2018©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power design of complex CMOS circuits is one of the major challenges that is being addressed and will be addressed in nanometer design era. With integration of millions and billions of transistors on a single chip, transistor density is drastically increasing that lead to more and more complexity in applications being implemented on a single chip. Design time is another major challenge that forces designers to address the need in a very short time optimizing chip performances. In order to ensure that the design is through in the first iteration, designers are banking on new methodologies and readymade solutions to optimize area, time and power. Hence, various power dissipation techniques for CMOS inverter circuit are investigated here.
Keywords: Low Power Design, CMOS Circuits, Millions and Billions of Transistors, Transistor Density, Optimize Area, Time and Power.